Lockheed Martin Receives Contract to Demonstrate a C-RAM Interceptor System

Released on Thursday, March 06, 2008

DALLAS, TX, March 6th, 2008 -- Lockheed Martin [NYSE: LMT] has received an $8.6 million Science and Technology contract from the U.S. Army Research and Development Command (RDECOM) Missiles and Aviation Research and Development Center (AMRDEC) to demonstrate a Counter Rockets, Artillery and Mortar (C-RAM) interceptor system. Work on the contract will be completed by November 2008.

This activity is part of an AMRDEC effort to develop and demonstrate critical counter-fire technologies, bridging the gap between existing C-RAM capabilities and its overall objective extended area air defense system vision, which addresses short-range air defense against certain types of threats. During the development phase, which is called the Extended Area Protection and Survivability (EAPS) program, efforts will focus on developing and leveraging technologies to provide mobile, hemispherical extended area protection from RAM threats.

"Lockheed Martin will leverage our legacy of combat-proven kinetic energy, hit-to-kill successes that stretch back decades," said Mike Trotsky, vice president of Air & Missile Defense at Lockheed Martin Missiles and Fire Control. "By giving our Warfighters the overwhelming lethality advantage of hit-to-kill technology, coupled with precision engagement, we can provide them with the tools they need to achieve mission success."

Lockheed Martin's concept features a compact, vertically launched missile that offers the Warfighter significant operational and tactical advantages against RAM threats. The system encompasses the interceptor, fire control sensor, launcher and battle manager, and will ultimately interface with the latest battlefield surveillance systems. The Lockheed Martin team includes Lockheed Martin Missiles and Fire Control, Lockheed Martin Maritime Systems & Sensors and Lockheed Martin Space Systems Company.

The contract calls for the design, fabrication, integration and test of the prototype hardware, and is structured as a base award to be followed by four options aligning to the five phases of the program. Phase 1 culminates in a Preliminary Design Review. Phase 2 includes Hardware-in-the-Loop and a Critical Design Review, paving the way to demonstrating intercepts of individual RAM targets in Phase 3 and multiple simultaneous intercepts of RAM targets in Phase 4. Phase 5 is a risk-reduction phase in anticipation of the System Development and Demonstration program, ultimately leading to a production program providing a significant improvement in C-ram capabilities.